1. Field of the Invention
The present invention relates to a time division switching system for use in a network capable of simultaneously handling both telephone exchange service and non-telephone service including high speed and broad band communication service.
2. Description of the Prior Art
A time division switching system switches connections between two channels of two different time division multiplex communication paths.
Known time division switches utilize a memory switch and a control memory. Input signals on the channels of a number of input lines, for instance, N lines, are written into the memory switch. The signals are then read out in a prescribed sequence (which is different from the sequence of writing the input signals into this memory switch). The signals are then output into the channels on the N different output lines. This enables the N communication lines which are connected to the output side to be connected with the N communication lines connected on the input side. The line may be so interconnected in any desired combination, on a channel basis.
The control memory is used to supply read addresses for the memory switch. Read addresses for the N lines, i.e., N such addresses, are written into the control memory and read out in a prescribed sequence and supplied to the memory switch.
To change a connection between channels, the corresponding read address written into the control memory is altered.
A time frame is a complete round of actions to sequentially store all the signals for said N lines and to read these signals for the N lines in a prescribed sequence with the memory switch If the time length of this single frame is selected to be 125 microseconds and if signals for a single line (or a single channel) are eight-bit digital signals, 8 (bits) / 125 (microseconds)=64 kilo bits (Kb) per line are switched (for instance in a telephone exchange) each second. Such a switching process will be hereinafter referred to as "64 K b/s" (second) switching.
However, if data transmission is to be achieved through a data terminal, having a transmission speed with is higher than 64 K b/s, connected to a 64 K b/s switching system, a series of data will be split into two or more time slots within a frame and separately transmitted (two time slots are used if the bit rate is 64 K b/s.times.2=228 K b/s). Since these separate groups of data (multi-element data) have close relationships and continuity among one another within the same time frame, they have to be within the same frame when inputted or output by a time division switch. However, a conventional time division, switch cannot preserve the same sequence of signals on both the input side and the output side. Thus, high speed data switching cannot be achieved in such an instance unless some special arrangement is made.
The following description concerns, as an example, a case in which a multiplex-time-division communication path of 128 channels per frame is handled with a time division switch. FIG. 1 illustrates a typical three-stage time division switching system having a primary switch PSW (time division switch), a secondary switch SSW (space division switch) and a tertiary switch TSW (time division switch). In the time division switches constituting the primary and tertiary switches, eight-bit data of one of the 128 channels is allocated for each time side on the input slot, and is inserted into, any . desired time slot on the output side, to become the output signal.
As illustrated in FIG. 2(a), there are two mutually related data X1 (8 bits) and X2 (8 bits) (multi-element data), i.e., two data of 64 K b/s.times.2, belonging to a single frame in the input time slots "ITS's" No. 0 and No. 4, respectively. If the time division switch inserts these data Xl and X2 into unoccupied output time slots "OTS's" No. 0 and No. 6, respectively, to be output, these data X1 and X2 will be output in the same frame so that their relativity will be preserved. However, if OTS No. 0 and No. 1 are selected, as shown in FIG. 2(b), for outputting two 64 K b/s data X1 and X2, respectively, the data X2 cannot be written into the memory switch in time for it to be read out (insertion into OTS No. 1). Therefore, the data X2 in the preceding frame (a cycle before) will always be output into OTS No. 1. The sequence between the X1 and X2 cannot be preserved. The relativity between them cannot be maintained at the data terminal on the receiving side. If an algorithm of software is designed to select OTS's in the time division switch so as to always read out the data after their writing into the memory switch within the same frame, as shown in FIG. 2(a), the sequence and relativity will be preserved even in the switching is 64 K b/s.times.2. However, such software will invite increases in the time required for processing a selection of unoccupied time slot and in the block ratio, resulting in reduction of the processing capacity of the switching system.
Meanwhile, U.S. patent application Ser. No. 07/187,258 filed Apr. 28, 1988 by the same applicant, describes an example of double-buffered time division switching system in which two memory switches are used, one in the read mode while the other is in the write mode. A use of such a time division switch for switching 64 K b/s.times.n data, as referred to above, would make it possible to preserve the sequence and relativity among the data. However, since this system needs two memory switches in each time division switch, the entire system is expensive. Moreover, any existing network using conventional time division switches would require a replacement of all the time division switch or a conversion into a double-buffered structure. This would be too expensive and accordingly unadvantageous for a network whose volume of the multi-element data traffic is small.